It covers step 5 and 6 of the work flow depicted in Figure 4.2 of Chapter 4 and elaborated in the contributions in its succeeding section. This Chapter presents a very novel approach of linking the Modelsim and Simulink of Matlab for up-loading the VHDL design that is used for cross verifying the results of all arithmetic operations of addition/subtraction, division and multiplication by simulation in Modelsim wave window of Matlab after creating the simulink model and subsystem. Once the link between Modelsim and Matlab/simulink is created and the VHDL design is up-loading on to the simulink the same then can be optimized to get the optimal results in respect of power, area and speed.
In the work carried out on VHDL code generation with Matlab /Simulink, there is hardly any reference of work in the literature for linking the VHDL design system on to the Matlab/simulink.
In the recent, Abdullah and Hadi (2010), Mishra, Save and Rane (2011) and Valenzuela and Abdullah (2011) have used the graphical Matlab/Simulink environment for FPGA emulation, ASIC design, verification and chip testing. It also shows resource utilization report at the algorithm level, approximately what hardware resources are needed to implement the design, in terms of adders, multipliers, and RAMs. In addition to generating synthesizable HDL code, HDL Coder™ also generates various reports, including a traceability report that helps to navigate between the Matlab code and the generated HDL code. One can generate either VHDL or Verilog code that implements the Matlab design. The HDL Code Generation step in MATLAB generates HDL code from the fixed-point Matlab code. CHAPTER V SIMULATION AND VERIFICATION OF VHDL DESIGN OF 32-BIT FPAU IN SIMULINK
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